RTL Design Engineer, Multimedia and Machine Learning Accelerators

RTL Design Engineer, Multimedia and Machine Learning Accelerators

corporate_fare Google place Mountain View, CA, USA

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• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  
• 8 years of experience designing RTL digital logic using SystemVerilog for FPGA/Application-Specific Integrated Circuits (ASICs) or equivalent practical experience.
• Experience with a scripting language such as Perl or Python.
• Experience in area, power and performance.

Preferred qualifications

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  
• Experience implementing Graphics Processing Unit (GPU), Multimedia Intellectual Property (IP)(Camera, Display or COdec) or Machine Learning IP.
• Experience with ASIC design method...