Job Description
RTL Designer / ASIC Design Engineer
We are looking for a
Senior ASIC Design Engineer
to own the
end-to-end design of critical AI ASIC subsystems
– from PLLs and compute clusters to interconnects and multi-die orchestration. The RTL you create will become production silicon, powering real-world AI workloads faster and more efficiently. In this role, every
microsecond, watt, and millimeter
directly impacts AI economics at scale
Description
Responsibilities
Lead the
end-to-end design
of complex ASIC subsystems, including specification, architectural exploration, IP evaluation/selection, integration, verification planning, and post-silicon validation.
Drive
architecture and micro-architecture trade-offs
across features, performance, power, and area. Define clean interfaces and deliver production-quality RTL (Verilog/SystemVerilog).
Implement and verify designs at both block and subsystem...
We are looking for a
Senior ASIC Design Engineer
to own the
end-to-end design of critical AI ASIC subsystems
– from PLLs and compute clusters to interconnects and multi-die orchestration. The RTL you create will become production silicon, powering real-world AI workloads faster and more efficiently. In this role, every
microsecond, watt, and millimeter
directly impacts AI economics at scale
Description
Responsibilities
Lead the
end-to-end design
of complex ASIC subsystems, including specification, architectural exploration, IP evaluation/selection, integration, verification planning, and post-silicon validation.
Drive
architecture and micro-architecture trade-offs
across features, performance, power, and area. Define clean interfaces and deliver production-quality RTL (Verilog/SystemVerilog).
Implement and verify designs at both block and subsystem...
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