Job Description
RTL/FPGA Design Engineer
Project Duration: 12 Months + chances of further extension.
Base pay range
CA$110.00/hr - CA$135.00/hr
Job Description
Digital ASIC/FPGA Designer with at least 15 years of experience and a bachelor’s degree in engineering o...
Apply for this Position
Ready to join LanceSoft, Inc.? Click the button below to submit your application.
Submit Application