Job Description


Role Description

Role: Senior Engineer / Lead – Analog & High-Speed Layout

Experience: 3–8 years

Domain: High-Speed I/O, UCIe, DDR, SerDes, Chip-to-Chip, Mixed-Signal IP

Location: Bangalore

We are looking for a highly skilled Analog / Mixed-Signal Layout Engineer to work on advanced FinFET nodes (3nm, 4nm, 5nm, 7nm) for high-speed interface IPs such as UCIe, DDR5/LPDDR, SerDes, C2C, and PHYs.

The candidate will be responsible for full-custom layout from floorplan to sign-off, delivering high-performance, low-noise, DFM-clean layouts for cutting-edge SoCs and chiplet-based architectures


Skills Required
SoCs, C2C, SERDES

Apply for this Position

Ready to join ARF Design Pvt Ltd? Click the button below to submit your application.

Submit Application