Senior ASIC Design Engineer: RTL, Timing & Verification

A leading design services company in Ottawa is seeking an experienced ASIC Design Engineer with at least 8 years in the field. Responsibilities include creating and integrating RTL and C code, conducting testing and debugging, and participating in design reviews. Candidates should have strong proficiency in System Verilog and solid experience with digital synthesis and verification methods. This role promotes collaboration within a motivated team environment.
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