Senior ASIC RTL Engineer

The Senior ASIC Engineer will be responsible for RTL design, subsystem/IP integration, and ensuring high-quality SoC implementations. The role involves working with multiple IP blocks, performing static checks, supporting synthesis, and collaborating with verification, DFT, and software teams to resolve design queries.

Key Responsibilities

• Design and implement SoC subsystems and IP using Verilog/SystemVerilog.
• Perform subsystem/cluster and SoC-level IP integration.
• Conduct RTL quality checks including linting and clock domain crossing (CDC) analysis.
• Support synthesis, timing analysis, and low-power optimizations.
• Apply knowledge of AMBA bus protocols (AXI, AHB, ATB, APB) in design and integration.
• Work with interface protocols including PCIe, DDR, Ethernet, I2C, UART, and SPI.
• Set up and utilize tools like Spyglass (Lint/CDC), Synopsys Design Compiler (DC), Verdi/Xcellium.
• Write and maintain scripts using Ma...