Job Description

Overview

We are looking for an experienced Senior Design Engineer to drive the RTL-to-GDSII flow , focusing on timing analysis, floor-planning, place and route, timing closure, power analysis, and power grid optimization for mature and advanced technology nodes. This role involves backend design implementation for ASIC/FPGA , resource planning , team development , and project leadership to ensure successful client deliveries.

Key Responsibilities

  • Develop and implement low-power physical designs , including logic synthesis, STA, power analysis, IR drop, EM, and verification .
  • Identify and resolve power and performance issues , driving methodology improvements.
  • Conduct PPA benchmarking and ensure robustness of design flow.
  • Lead and manage design projects , ensuring on-time, high-quality deliverables .
  • Provide mentorship,...

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