Job Description
Job Description:
*Experience: 5+yrs of SOC Verification
*Own UVM-based constrained-random verification for complex SoC/IP subsystems.
*Develop testbenches, sequences, scoreboards, and checkers; close coverage (FC/CC/SC).
*Must have SystemVerilog/UVM, assertions (SVA), functional coverage...
*Experience: 5+yrs of SOC Verification
*Own UVM-based constrained-random verification for complex SoC/IP subsystems.
*Develop testbenches, sequences, scoreboards, and checkers; close coverage (FC/CC/SC).
*Must have SystemVerilog/UVM, assertions (SVA), functional coverage...
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