Job Description
Job Description
Position: Design Verification Engineer – PCIe / CXL Gen 5 & Gen 6
Company: Silicon Patterns
Location: Bangalore
Experience: 5–12+ Years (can be adjusted)
Notice Period: Immediate to 90 Days
Role Overview
Silicon Patterns is looking for a highly skilled Design Verification Engineer with strong expertise in PCIe and CXL protocols (Gen 5 & Gen 6). The role involves end-to-end verification of high-speed interconnect IPs and So Cs, working closely with design, architecture, and validation teams.
Key Responsibilities
- Develop and execute UVM-based verification environments for PCIe and CXL IPs (Gen 5 / Gen 6)
- Verify PCIe/CXL protocol layers (PHY, Link, Transaction layers)
- Create and maintain test plans, coverage models, assertions, and scoreboards
- Perform functional, regression, and corner-case verification
- Debug protocol-level issues using System Verilog, UVM, and protocol analyzers
- Collaborate with RTL designers to resolve functional and performance issues
- Support So C-level integration verification involving PCIe/CXL subsystems
- Analyze failures and ensure coverage closure
- Contribute to verification methodology improvements and automation
Required Skills & Qualifications
- Strong experience in Design Verification using System Verilog and UVM
- Hands-on expertise in PCIe Gen 5 / Gen 6 (LTSSM, Equalization, Flow Control, AER, SR-IOV, etc.)
- Good understanding of CXL (CXL.io, CXL.cache, CXL.mem) protocols
- Experience with verification IPs (VIPs) for PCIe/CXL
- Proficiency in assertion-based verification (SVA)
- Strong debugging skills at block and So C level
- Solid understanding of digital design fundamentals
- Experience with simulation tools (VCS, Questa, Xcelium, etc.)
Company Overview — Silicon Patterns
Silicon Patterns is a specialized semiconductor engineering services company delivering comprehensive solutions across the entire silicon design and development lifecycle. The company excels in pre-silicon and post-silicon engineering services, helping clients accelerate product development while ensuring high quality and first-pass silicon success.
With its headquarters in Hyderabad and offices in Bangalore and Raipur, Silicon Patterns also supports global teams in Malaysia and beyond, serving customers across Wireless, Io T, Automotive, and advanced computing domains.
Silicon Patterns offers end-to-end semiconductor solutions including:
- RTL Design & IP Development
- Design Verification (DV) using modern methodologies like UVM/System Verilog
- Emulation, Pre- & Post-Silicon Validation
- Physical Design (PD) & DFT
- System C Modeling, Prototyping, and Silicon Bring-Up Support
Position: Design Verification Engineer – PCIe / CXL Gen 5 & Gen 6
Company: Silicon Patterns
Location: Bangalore
Experience: 5–12+ Years (can be adjusted)
Notice Period: Immediate to 90 Days
Role Overview
Silicon Patterns is looking for a highly skilled Design Verification Engineer with strong expertise in PCIe and CXL protocols (Gen 5 & Gen 6). The role involves end-to-end verification of high-speed interconnect IPs and So Cs, working closely with design, architecture, and validation teams.
Key Responsibilities
- Develop and execute UVM-based verification environments for PCIe and CXL IPs (Gen 5 / Gen 6)
- Verify PCIe/CXL protocol layers (PHY, Link, Transaction layers)
- Create and maintain test plans, coverage models, assertions, and scoreboards
- Perform functional, regression, and corner-case verification
- Debug protocol-level issues using System Verilog, UVM, and protocol analyzers
- Collaborate with RTL designers to resolve functional and performance issues
- Support So C-level integration verification involving PCIe/CXL subsystems
- Analyze failures and ensure coverage closure
- Contribute to verification methodology improvements and automation
Required Skills & Qualifications
- Strong experience in Design Verification using System Verilog and UVM
- Hands-on expertise in PCIe Gen 5 / Gen 6 (LTSSM, Equalization, Flow Control, AER, SR-IOV, etc.)
- Good understanding of CXL (CXL.io, CXL.cache, CXL.mem) protocols
- Experience with verification IPs (VIPs) for PCIe/CXL
- Proficiency in assertion-based verification (SVA)
- Strong debugging skills at block and So C level
- Solid understanding of digital design fundamentals
- Experience with simulation tools (VCS, Questa, Xcelium, etc.)
Company Overview — Silicon Patterns
Silicon Patterns is a specialized semiconductor engineering services company delivering comprehensive solutions across the entire silicon design and development lifecycle. The company excels in pre-silicon and post-silicon engineering services, helping clients accelerate product development while ensuring high quality and first-pass silicon success.
With its headquarters in Hyderabad and offices in Bangalore and Raipur, Silicon Patterns also supports global teams in Malaysia and beyond, serving customers across Wireless, Io T, Automotive, and advanced computing domains.
Silicon Patterns offers end-to-end semiconductor solutions including:
- RTL Design & IP Development
- Design Verification (DV) using modern methodologies like UVM/System Verilog
- Emulation, Pre- & Post-Silicon Validation
- Physical Design (PD) & DFT
- System C Modeling, Prototyping, and Silicon Bring-Up Support
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