Job Description
Senior Design Verification Engineer with strong expertise in PCIe Gen5/Gen6, System Verilog, and UVM to drive IP/So C-level verification for high‑speed interfaces and ensure first‑time‑right silicon.
Exp-6+years
Location- Bengaluru, Hyderabad, Noida
Key responsibilities:
- Own verification strategy and test plan for PCIe Gen5/Gen6 controller/IP at block, subsystem, and So C level.
- Architect, develop, and maintain UVM‑based verification environments, agents, scoreboards, and coverage for PCIe and related high‑speed interfaces.
- Develop constrained‑random and directed tests in System Verilog/UVM to validate protocol features, LTSSM states, power management, error handling, and link training for Gen5/Gen6.
- Collaborate closely with RTL, architecture, and validation teams to refine specifications, review micro‑architecture, and close functional and code coverage.
- Debug complex failures using simulation, waveforms, assertions, and protocol analyzers; drive root‑cause and issue closure with cross‑functional teams.
- Integrate and use PCIe VIP, checkers, and protocol compliance suites; ensure adherence to PCIe Base specifications and ecosystem interoperability requirements.
- Contribute to verification methodology improvements, scripting/automation for regressions, and best practices for high‑speed protocol verification.
- Mentor junior engineers on UVM, PCIe protocol concepts, and debug techniques as a technical go‑to person in the team.
Required skills and experience
- 6+ years of ASIC/So C design verification experience with a strong focus on PCIe Gen5/Gen6 or other high‑speed serial protocols.
- Solid hands‑on expertise with System Verilog and UVM, including building reusable environments, sequences, agents, and coverage models.
- Strong understanding of PCIe protocol (layers, TLP/DLLP, LTSSM, flow control, error reporting, link training, and equalization), preferably Gen5/Gen6.
- Proven experience in constrained‑random verification, functional/code/MC coverage, assertions (SVA), and coverage closure on complex IP/So C designs.
- Proficiency with industry‑standard simulators and regression environments; good scripting skills in Python/Perl/Shell for automation.
- Strong debug skills, problem‑solving attitude, and ability to work in fast‑paced, cross‑site teams.
- Experience with related protocols like CXL, NVMe over PCIe, or AMBA/AXI interconnects.
- Exposure to post‑silicon validation, FPGA/emulation, or lab‑based PCIe bring‑up and protocol analyzers.
- Knowledge of RTL design concepts, timing, and low‑power features for high‑speed I/O subsystems.
Education:
- Bachelor’s or Master’s degree in Electronics, Electrical, Computer Engineering, or VLSI with a strong digital design and verification background.
About Us:
Silicon Patterns is a specialized engineering services company with deep expertise in pre-silicon and post-silicon design and verification. We deliver end-to-end semiconductor and embedded system solutions covering RTL Design, System C Modeling, Emulation, Design Verification (DV), Physical Design (PD), Design for Testability (DFT), and Pre- & Post-silicon Validation — helping clients achieve faster, more reliable product development. Headquartered in Hyderabad, with offices in Bangalore and Raipur, and supported by our skilled engineering teams in Malaysia, we serve global clients through flexible engagement models like Time & Materials (T&M), Offshore Development Centers (ODC), Subcontracting, and Build-Operate-Transfer (BOT). Our expertise spans VLSI and Embedded Systems, with a strong focus on Wireless, Io T, and Automotive domains. We also work on advanced technologies including HBM3/3 E workloads, AI/ML, Gen AI/LLMs, and edge computing. At Silicon Patterns, we’re committed not only to technical excellence but also to maintaining a strong work-life balance for our teams because great engineering starts with well-supported people.
Website
Exp-6+years
Location- Bengaluru, Hyderabad, Noida
Key responsibilities:
- Own verification strategy and test plan for PCIe Gen5/Gen6 controller/IP at block, subsystem, and So C level.
- Architect, develop, and maintain UVM‑based verification environments, agents, scoreboards, and coverage for PCIe and related high‑speed interfaces.
- Develop constrained‑random and directed tests in System Verilog/UVM to validate protocol features, LTSSM states, power management, error handling, and link training for Gen5/Gen6.
- Collaborate closely with RTL, architecture, and validation teams to refine specifications, review micro‑architecture, and close functional and code coverage.
- Debug complex failures using simulation, waveforms, assertions, and protocol analyzers; drive root‑cause and issue closure with cross‑functional teams.
- Integrate and use PCIe VIP, checkers, and protocol compliance suites; ensure adherence to PCIe Base specifications and ecosystem interoperability requirements.
- Contribute to verification methodology improvements, scripting/automation for regressions, and best practices for high‑speed protocol verification.
- Mentor junior engineers on UVM, PCIe protocol concepts, and debug techniques as a technical go‑to person in the team.
Required skills and experience
- 6+ years of ASIC/So C design verification experience with a strong focus on PCIe Gen5/Gen6 or other high‑speed serial protocols.
- Solid hands‑on expertise with System Verilog and UVM, including building reusable environments, sequences, agents, and coverage models.
- Strong understanding of PCIe protocol (layers, TLP/DLLP, LTSSM, flow control, error reporting, link training, and equalization), preferably Gen5/Gen6.
- Proven experience in constrained‑random verification, functional/code/MC coverage, assertions (SVA), and coverage closure on complex IP/So C designs.
- Proficiency with industry‑standard simulators and regression environments; good scripting skills in Python/Perl/Shell for automation.
- Strong debug skills, problem‑solving attitude, and ability to work in fast‑paced, cross‑site teams.
- Experience with related protocols like CXL, NVMe over PCIe, or AMBA/AXI interconnects.
- Exposure to post‑silicon validation, FPGA/emulation, or lab‑based PCIe bring‑up and protocol analyzers.
- Knowledge of RTL design concepts, timing, and low‑power features for high‑speed I/O subsystems.
Education:
- Bachelor’s or Master’s degree in Electronics, Electrical, Computer Engineering, or VLSI with a strong digital design and verification background.
About Us:
Silicon Patterns is a specialized engineering services company with deep expertise in pre-silicon and post-silicon design and verification. We deliver end-to-end semiconductor and embedded system solutions covering RTL Design, System C Modeling, Emulation, Design Verification (DV), Physical Design (PD), Design for Testability (DFT), and Pre- & Post-silicon Validation — helping clients achieve faster, more reliable product development. Headquartered in Hyderabad, with offices in Bangalore and Raipur, and supported by our skilled engineering teams in Malaysia, we serve global clients through flexible engagement models like Time & Materials (T&M), Offshore Development Centers (ODC), Subcontracting, and Build-Operate-Transfer (BOT). Our expertise spans VLSI and Embedded Systems, with a strong focus on Wireless, Io T, and Automotive domains. We also work on advanced technologies including HBM3/3 E workloads, AI/ML, Gen AI/LLMs, and edge computing. At Silicon Patterns, we’re committed not only to technical excellence but also to maintaining a strong work-life balance for our teams because great engineering starts with well-supported people.
Website
Apply for this Position
Ready to join ? Click the button below to submit your application.
Submit Application