Senior design verification engineer

Job Location: HyderabadNotice Period: 15 days to 30 DaysMinimum: 4 YearsKey Responsibilities:Developing test plansCoding and bring up of asm, c++ testsUVM test bench components coding and maintainingDebugging regression failsProtocol: DDR, PCIE, USB, MIPIPreferred Experience:Should have worked on Processor based System or Sub-system level verificationHands on experience with assembly, UVM, SV, C++Experience in developing complex test bench/model in UVM, Verilog, System VerilogHands on experience in developing test plans, coverage closureAbility to code readable, maintainable and verifiable code using UVM, SV, Strong digital design conceptsExperience in developing asm/C++ tests will be an added advantageExperience in Power Management, Clock, Reset will be an added advantageExperience/Knowledge DPI Interface, Ruby/Perl script programming skills will be an added advantage