Senior Design Verification Engineer - SystemVerilog/UVM Expert

A global semiconductor leader is seeking a Senior Design Verification Engineer in Valencia, Spain. This role involves defining and executing verification strategies, developing and debugging tests using System Verilog and UVM, and collaborating with cross-functional teams to ensure high design quality. Ideal candidates will have a Master's in Engineering, experience in object-oriented programming, and familiarity with various simulation tools. This position offers opportunities for professional growth in a dynamic environment.
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