Job Description
About Analog Devices
Analog Devices, Inc. (NASDAQ: ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at and on and.
Responsibilities
DFT architecture definitionUnderstand SoC architecture and test requirements.Work very closely with the lead Product/Test engineering throughout the DFT definition phase to determine efficient ways to optimize test cost and achieve high test coverage.Drive and optimize DFT architecture for high performance and efficiency:SCAN – scan partition, compression, at-speed, IR and low powerMBIST for memoriesJTAG boundary scan insertionHandle responsibilities pertaining to both block and top-level activities in Hierarchical Scan. ImplementationDevelop / Upgrade SCAN & MBIST Insertion flowsDevelop appropriate timing constraints for SCAN/MBIST modes and debug timing violationsATPG flow implementation catering to various fault models, test pattern generationSCAN , MBIST & BSCAN Pattern SimulationSolutions to test analog macros Post-Silicon bring-up/supportWork with Evaluation/Test Engineering team to bring-up patterns on ATEWork on failure analysis as requiredWork with the Operation team on test cost and yield improvement Improve DFT methodology to be in sync with latest best practices and technology in the industry Work closely with physical design team throughout the development cycle. Should be able to guide newly inducted team members on their bring-up on flow, methodology and execution methods in all aspects of DFT. Requirements
4-8 years of industry experience in DFT domain. Must have experience in bringing atleast one or two products to successful production from architecture phase, scan implementation and simulations. Must have hands-on experience working on post-silicon activities. Having working experience with tessent DFT (SCAN, Mbist, Lbist, OCC, EDT, SSN, Boundary Scan) will be preferred. Exceptional interpersonal and communication skills are critical for working, influencing and collaborating with product development groups and CAD tool teams spread across the globe. Scripting skills in Perl/Python/TCL and a good command over HDLs. Candidates with exposure to deep submicron effects and low power implementation using UPF/CPF will be at an advantage. Candidates with experience using Cadence digital implementation tools (Genus, Tempus) would be preferred. Prior experience of timing closure/physical design will be an added plus. Job Req Type: ExperiencedRequired Travel: Yes, 10% of the timeShift Type: 1st Shift/Days
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