Job Description

Description

We are looking for a Senior Digital Design Verification Engineer – Germany

Tasks and responsibilities

  • Define verification strategy for digital and mixed-signal IPs as per system requirements. Define testbench architecture and partition, develop verification plan, and interact with digital, mixed-signal and analog design engineers for feature extraction.

  • Apply state-of-art methodologies (UVM, Formal Verification) and develop efficient and reusable verification environments and testbench components. Develop IP-level and system-level testbenches maximizing coverage and re-use. Develop constraint random tests, checkers and coverage models based on IC specifications.

  • Define infrastructure to support mixed-signal verification and analog/real-number behavioral modelling.

  • Support/Perform execution of verification plans, which includes environment setup, regression running (RTL and gate-level...

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