Senior Digital Verification Engineer

You Are:

You are an accomplished engineer with a passion for digital and mixed-signal verification. Your career is marked by a relentless drive to excel in complex environments, where your expertise in SystemVerilog and UVM-based testbench development sets you apart. You thrive in collaborative settings, actively contributing to cross-functional teams and fostering an inclusive, supportive culture. Your strong analytical skills, attention to detail, and creative problem-solving abilities enable you to navigate intricate verification challenges and deliver robust solutions.

What You’ll Be Doing:

• Develop comprehensive testplans for complex mixed-signal IP, detailing verification strategies and coverage goals.
• Design and implement UVM-based testbenches using constraint-random verification methodologies to ensure thorough validation.
• Enhance and modify testbench components such as scoreboards, agents, and sequences to support evolv...