Job Description
LTTS is looking for DV engineers with 7+ years of experience for lead role...detailed JD is below mentioned.
8/10+ of hands-on experience in Stem Verilog/UVM methodology and/or C/C++ based verification
8/ 10+ experience in IP/sub-stem and/or So C level verification based on Stem Verilog UVM/OV...
8/10+ of hands-on experience in Stem Verilog/UVM methodology and/or C/C++ based verification
8/ 10+ experience in IP/sub-stem and/or So C level verification based on Stem Verilog UVM/OV...
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