Senior dv engineers (uvm/verliog)

LTTS is looking for DV engineers with 7+ years of experience for lead role...detailed JD is below mentioned. 8/10+ of hands-on experience in Stem Verilog/UVM methodology and/or C/C++ based verification 8/ 10+ experience in IP/sub-stem and/or So C level verification based on Stem Verilog UVM/OVM bas...