Job Description
Job Title: Physical Design Engineer
Experience: 4+ Years
Location: Coimbatore
Employment Type: Full‑time
Required Qualifications
Bachelor’s or Master’s degree in Electronics/Electrical/Computer Engineering or related field.
4+ years of hands‑on experience in ASIC/So C Physical Design.
Strong understanding of physical design flows (RTL2 GDSII).
Experience with EDA tools such as Synopsys , Cadence , Mentor – e.g., IC Compiler, Innovus, Prime Time, Tempus, Hercules, etc.
Proficiency in STA, timing closure techniques, clocking strategies, congestion analysis.
Good scripting skills in Tcl , Perl , Python , or Shell.
Knowledge of power analysis, floorplanning, ECO flow, clock tree synthesis, and routing optimization
Key Responsibilities
Execute physical design implementation flow from RTL to GDSII for complex So C/ASIC projects.
Perform floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and optimization.
Conduct timing closure using STA tools and methodologies, including multi‑corner/multi‑mode analysis (MCMM).
Resolve congestion, IR drop, electromigration (EM), and signal integrity challenges.
Perform DRC/LVS/ERC checks and collaborate with CAD team for ECO and fix strategies.
Work closely with RTL, synthesis, verification, and backend teams to ensure successful tape‑out.
Drive performance, area, power (PPA) optimization based on constraints and design goals.
Develop and maintain RTL constraints, SDC, and scripts for design implementation.
Support design for test (DFT) insertion and validation.
Experience: 4+ Years
Location: Coimbatore
Employment Type: Full‑time
Required Qualifications
Bachelor’s or Master’s degree in Electronics/Electrical/Computer Engineering or related field.
4+ years of hands‑on experience in ASIC/So C Physical Design.
Strong understanding of physical design flows (RTL2 GDSII).
Experience with EDA tools such as Synopsys , Cadence , Mentor – e.g., IC Compiler, Innovus, Prime Time, Tempus, Hercules, etc.
Proficiency in STA, timing closure techniques, clocking strategies, congestion analysis.
Good scripting skills in Tcl , Perl , Python , or Shell.
Knowledge of power analysis, floorplanning, ECO flow, clock tree synthesis, and routing optimization
Key Responsibilities
Execute physical design implementation flow from RTL to GDSII for complex So C/ASIC projects.
Perform floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and optimization.
Conduct timing closure using STA tools and methodologies, including multi‑corner/multi‑mode analysis (MCMM).
Resolve congestion, IR drop, electromigration (EM), and signal integrity challenges.
Perform DRC/LVS/ERC checks and collaborate with CAD team for ECO and fix strategies.
Work closely with RTL, synthesis, verification, and backend teams to ensure successful tape‑out.
Drive performance, area, power (PPA) optimization based on constraints and design goals.
Develop and maintain RTL constraints, SDC, and scripts for design implementation.
Support design for test (DFT) insertion and validation.
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