Job Description
Position:
Senior Engineer (Level 1)
Job Description:
Principal Accountabilities
* Responsible for floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing, extraction, timing closure, DFT, signal integrity, physical verification and DFM.
* Execute block level place and route assignments from Netlist through GDS flow.
* Perform full chip implementation of complex SoCs (RTL-to-GDSII) if needed.
* Close STA timing across all corners and modes for blocks and should be able to generate ECO independently .
* Work with design teams for closing CTS, IO timing, DFT timing.
* Responsible for digital design automation, flow-automation and regression across RTL-to-GDSII.
Job Complexity
Job complexity may vary among jobs within this job level and will align with one of the job complexities listed below:
(1) Incumbent has knowledge and experience in own discipline and may still be acquiring higher level know...
Senior Engineer (Level 1)
Job Description:
Principal Accountabilities
* Responsible for floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing, extraction, timing closure, DFT, signal integrity, physical verification and DFM.
* Execute block level place and route assignments from Netlist through GDS flow.
* Perform full chip implementation of complex SoCs (RTL-to-GDSII) if needed.
* Close STA timing across all corners and modes for blocks and should be able to generate ECO independently .
* Work with design teams for closing CTS, IO timing, DFT timing.
* Responsible for digital design automation, flow-automation and regression across RTL-to-GDSII.
Job Complexity
Job complexity may vary among jobs within this job level and will align with one of the job complexities listed below:
(1) Incumbent has knowledge and experience in own discipline and may still be acquiring higher level know...
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