Senior Functional Verification Engineer

We have an exciting opportunity available for a Senior Functional Verification Engineer based in Spain.

Role Overview

We are seeking a Senior Functional Verification Engineer to work closely with architecture, design, physical implementation, and software teams to ensure our systems meet the highest quality standards. The role involves high-level modeling, UVM-based verification, HW/SW co-debug, and simulation acceleration support.

Key Responsibilities

• Analyse system and architecture requirement documents to define and guide verification strategies.
• Develop and maintain verification environments using SystemVerilog, UVM, SystemC, and C++ (Stimulus, Checkers, Assertions, Trackers, Coverage).
• Execute verification plans, including design bring-up, regressions, and test debugging.
• Debug and root-cause issues using simulators, coverage tools, and close collaboration with design teams.
• Con...