Job Description

#Proxelera I We’re Hiring Senior / Principal ASIC Design Verification Engineers for Bangalore, Hyderabad and Delhi locations

Proxelera is expanding its Design Verification DV teams and we’re looking for passionate, hands-on Verification Engineers to work on cutting-edge SoC and ASIC designs.


Locations: Bangalore (Urban), Hyderabad, Delhi

Work Mode: Full-time | On-site

Open Positions

Sr. Lead / Principal / Manager – ASIC (SoC & Large Subsystems) DV 8–15+ years | Bengaluru

Senior / Principal DV Engineer – SoC / ASIC 10–15+ years | Bengaluru & Delhi

Senior DV Engineer 6–8 years | Bengaluru & Delhi

Low-Power SoC DV Engineer 5–10 years | Bengaluru

SoC DV Engineer 5–10 years | Bengaluru

IP DV Engineer 5–10 years | Bengaluru

DV Engineer 5-8 years | Hyderabad


About Proxelera

Proxelera is focused on making the chip development journey smoother and more predictable.

Proxelera specializes in RTL, ASIC, and SoC Verification, helping semiconductor teams deliver first-time-right silicon. With deep expertise across IP, subsystem, and full-chip verification, we work on complex designs spanning low-power SoCs, processors, interconnects, and high-performance accelerators. Our engineers leverage SystemVerilog, UVM, assertion-based verification, and coverage-driven methodologies to ensure quality, scalability, and predictable tapeouts.


If you’re open to exploring new opportunities, please apply via the link or share your updated resume at [email protected], or DM me / call at +91 96329 00829.

I’d be happy to discuss how these roles align with your experience and career goals.


Best regards,

Girish Nidyamale

Manager – Talent Acquisition

📞 +91 96329 00829

✉️ [email protected]

🔗 Let’s connect on LinkedIn: https://www.Linkedin.Com/in/girish-nidyamale-6127717

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