Senior Lead

ob Title: Physical Design Engineer

Experience: 4+ Years

Location: Bangalore

Employment Type: Full‑time

Required Qualifications

• Bachelor’s or master’s degree in Electronics/Electrical/Computer Engineering or related field.

• 4+ years of hands‑on experience in ASIC/SoC Physical Design .
• Strong understanding of physical design flows (RTL2GDSII).
• Experience with EDA tools such as Synopsys , Cadence , Mentor – e.g., IC Compiler, Innovus, Primetime, Tempus, Hercules, etc.
• Proficiency in STA, timing closure techniques, clocking strategies, congestion analysis.
• Good scripting skills in Tcl , Perl , Python , or Shell .
• Knowledge of power analysis, floor planning, ECO flow, clock tree synthesis, and routing optimization

Key Responsibilities

• Execute physical design implementation flow from RTL to GDSII for complex SoC/ASIC projects.
• Perform floor planning, power planning, placement, clock tree synthesis (CTS), routing, and optimization.
• Conduct timing closure using STA tools and methodologies, including multi‑corner/multi‑mode analysis (MCMM).
• Resolve congestion, IR drop, electromigration (EM), and signal integrity challenges.
• Perform DRC/LVS/ERC checks and collaborate with CAD team for ECO and fix strategies.
• Work closely with RTL, synthesis, verification, and backend teams to ensure successful tape‑out.
• Drive performance, area, power (PPA) optimization based on constraints and design goals.
• Develop and maintain RTL constraints, SDC, and scripts for design implementation.
• Support design for test (DFT) insertion and validation.
• Provide design documentation and participate in design reviews.