Senior/ Lead Design Verification Engineer

Hiring: Senior & Lead Design Verification Engineers

ACL Digital is looking for experienced Design Verification professionals to join our teams in Bangalore and Hyderabad . We are looking for proactive engineers who can drive IP and SoC verification cycles for cutting-edge semiconductor products.

Quick Overview

• Experience: 4 – 20 Years
• Location: Bangalore / Hyderabad (On-site/Hybrid as per company policy)
• Notice Period: Immediate to 30 Days ONLY (Candidates currently serving notice are also preferred)
• Education: B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or related fields.

Open Roles & Technical Requirements

Role 1: Design Verification Engineer (Mid-Senior)

• Experience: 4+ Years
• Proven track record in IP or SoC Design Verification .
• Mandatory expertise in SystemVerilog (SV) and UVM methodology .
• Ability to develop test benches and functional coverage models.

Role 2: Senior / Lead Verification Engineer

• Experience: 5+ to 20 Years
• Technical Proficiencies:
• Expertise in SystemVerilog/UVM and digital design concepts (RTL).
• Proficiency with industry-standard simulators: VCS, Questa, or Xcelium .
• Deep understanding of Coverage-Driven Verification (CDV) .
• Hands-on experience debugging complex verification environments.
• Preferred Skills (Good to Have):
• Experience with SoC-level verification and low-power verification (UPF/CPF).
• Knowledge of protocols: AMBA (AXI/AHB/APB), PCIe, USB, or DDR .
• Strong scripting skills in Python, Perl, or Shell for automation.
• Experience with SystemVerilog Assertions (SVA) .

Why Join Us?

At ACL Digital, you will work on complex, high-impact projects within the semiconductor domain, collaborating with global leads to push the boundaries of silicon design.

How to Apply

If you meet the experience criteria and are available to join within 30 days, please share your updated CV with:

Email:

Subject Line: Application for (Senior/Lead) DV Engineer - (Your Years of Exp) - (Your Current Location)