Job Description
Job Role: Physical Design Engineer- Senior/Lead
Location: Bangalore, Hyderabad, Noida and Ahmedabad
Experience Required: 5+
ROLE & RESPONSIBILITIES
- Engineer will be responsible for floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing, extraction, timing closure, DFT, Antenna fixing &signal integrity, Power grid analysis atc in ASIC PNR Flow
- Engineer will be responsible for executing the block level place and route assignments from Netlist through GDS flow
- Should be able to do full chip implementation of complex SoCs (RTL-to-GDSII), but it is not must.
- To close STA timing across all corners and modes for blocks and should be able to generate ECO independently.
- Will be responsible to Work with design teams for closing CTS, IO timing, DFT timing.
- Responsible for digital design automation, flow-automation and regression across RTL-to-GDSII.
- To ensure successful delivery of his block(s) to c...
Location: Bangalore, Hyderabad, Noida and Ahmedabad
Experience Required: 5+
ROLE & RESPONSIBILITIES
- Engineer will be responsible for floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing, extraction, timing closure, DFT, Antenna fixing &signal integrity, Power grid analysis atc in ASIC PNR Flow
- Engineer will be responsible for executing the block level place and route assignments from Netlist through GDS flow
- Should be able to do full chip implementation of complex SoCs (RTL-to-GDSII), but it is not must.
- To close STA timing across all corners and modes for blocks and should be able to generate ECO independently.
- Will be responsible to Work with design teams for closing CTS, IO timing, DFT timing.
- Responsible for digital design automation, flow-automation and regression across RTL-to-GDSII.
- To ensure successful delivery of his block(s) to c...
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