Job Description
Senior Physical Design Engineer
Experience: 6+ Years
Location: Bengaluru, India
Job Description:
We are looking for a highly skilled Senior Physical Design Engineer with 6+ years of hands-on experience to drive end-to-end physical design implementation for advanced So C designs. The ideal candidate will have strong expertise in RTL-to-GDSII flow, Pn R, timing closure, and Innovus-based implementation in advanced technology nodes.
Key Responsibilities:
- Own and execute RTL to GDSII physical design flow for complex So C / IP blocks
- Perform Floorplanning, Power Planning, Placement, CTS, Routing, and Signoff
- Drive Pn R implementation using Cadence Innovus
- Achieve timing closure across all modes and corners (setup, hold, MCMM)
- Handle clock tree synthesis (CTS) and clock optimization
- Perform physical verification, including DRC, LVS, IR-drop, EM analysis
- Work closely with STA, DFT, RTL, and Verification teams to resolve design issues
- Debug and fix timing, congestion, power, and routability issues
- Support tape-out activities and ensure high-quality deliverables
- Contribute to flow improvements, automation, and best practices
Required Skills & Qualifications:
- 6+ years of experience in Physical Design / Backend VLSI
- Strong hands-on experience with Cadence Innovus
- Expertise in Pn R (Place & Route) and Timing Closure
- Solid understanding of RTL-to-GDSII flow
- Strong knowledge of:
- Static Timing Analysis (STA)
- Clocking methodologies
- Power intent (UPF/CPF – good to have)
- Experience with advanced nodes (28nm / 16nm / 7nm / below) is a plus
- Proficiency in Tcl / Shell / Python scripting for flow automation
- Familiarity with signoff tools (Tempus, Prime Time, Voltus, Calibre – preferred)
Good to Have
- Experience with low-power design techniques
- Exposure to multi-voltage designs and power optimization
- Experience in full-chip integration
- Tape-out experience for production silicon
About Us:
Silicon Patterns is a specialized engineering services company with deep expertise in pre-silicon and post-silicon design and verification. We deliver end-to-end semiconductor and embedded system solutions covering RTL Design, System C Modeling, Emulation, Design Verification (DV), Physical Design (PD), Design for Testability (DFT), and Pre- & Post-silicon Validation — helping clients achieve faster, more reliable product development. Headquartered in Hyderabad, with offices in Bangalore and Raipur, and supported by our skilled engineering teams in Malaysia, we serve global clients through flexible engagement models like Time & Materials (T&M), Offshore Development Centers (ODC), Subcontracting, and Build-Operate-Transfer (BOT). Our expertise spans VLSI and Embedded Systems, with a strong focus on Wireless, Io T, and Automotive domains. We also work on advanced technologies including HBM3/3 E workloads, AI/ML, Gen AI/LLMs, and edge computing. At Silicon Patterns, we’re committed not only to technical excellence but also to maintaining a strong work-life balance for our teams because great engineering starts with well-supported people.
Website
Experience: 6+ Years
Location: Bengaluru, India
Job Description:
We are looking for a highly skilled Senior Physical Design Engineer with 6+ years of hands-on experience to drive end-to-end physical design implementation for advanced So C designs. The ideal candidate will have strong expertise in RTL-to-GDSII flow, Pn R, timing closure, and Innovus-based implementation in advanced technology nodes.
Key Responsibilities:
- Own and execute RTL to GDSII physical design flow for complex So C / IP blocks
- Perform Floorplanning, Power Planning, Placement, CTS, Routing, and Signoff
- Drive Pn R implementation using Cadence Innovus
- Achieve timing closure across all modes and corners (setup, hold, MCMM)
- Handle clock tree synthesis (CTS) and clock optimization
- Perform physical verification, including DRC, LVS, IR-drop, EM analysis
- Work closely with STA, DFT, RTL, and Verification teams to resolve design issues
- Debug and fix timing, congestion, power, and routability issues
- Support tape-out activities and ensure high-quality deliverables
- Contribute to flow improvements, automation, and best practices
Required Skills & Qualifications:
- 6+ years of experience in Physical Design / Backend VLSI
- Strong hands-on experience with Cadence Innovus
- Expertise in Pn R (Place & Route) and Timing Closure
- Solid understanding of RTL-to-GDSII flow
- Strong knowledge of:
- Static Timing Analysis (STA)
- Clocking methodologies
- Power intent (UPF/CPF – good to have)
- Experience with advanced nodes (28nm / 16nm / 7nm / below) is a plus
- Proficiency in Tcl / Shell / Python scripting for flow automation
- Familiarity with signoff tools (Tempus, Prime Time, Voltus, Calibre – preferred)
Good to Have
- Experience with low-power design techniques
- Exposure to multi-voltage designs and power optimization
- Experience in full-chip integration
- Tape-out experience for production silicon
About Us:
Silicon Patterns is a specialized engineering services company with deep expertise in pre-silicon and post-silicon design and verification. We deliver end-to-end semiconductor and embedded system solutions covering RTL Design, System C Modeling, Emulation, Design Verification (DV), Physical Design (PD), Design for Testability (DFT), and Pre- & Post-silicon Validation — helping clients achieve faster, more reliable product development. Headquartered in Hyderabad, with offices in Bangalore and Raipur, and supported by our skilled engineering teams in Malaysia, we serve global clients through flexible engagement models like Time & Materials (T&M), Offshore Development Centers (ODC), Subcontracting, and Build-Operate-Transfer (BOT). Our expertise spans VLSI and Embedded Systems, with a strong focus on Wireless, Io T, and Automotive domains. We also work on advanced technologies including HBM3/3 E workloads, AI/ML, Gen AI/LLMs, and edge computing. At Silicon Patterns, we’re committed not only to technical excellence but also to maintaining a strong work-life balance for our teams because great engineering starts with well-supported people.
Website
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