Job Description
Eximietas Design... !
We are Hiring: Senior Physical Design Engineers / Leads / Architects / Managers.
Experience:
6-25+ Years.
Locations:
Bengaluru, India.
San Jose (Bay Area), USA.
Austin, USA.
Eligibility (USA): U. S. Permanent Residents (Green Card holders).
About the Role:
We are looking for highly experienced Senior Physical Design Leads/Managers to collaborate with top-tier semiconductor customers on advanced technology nodes.
Qualifications:
Bachelor’s or Master’s degree in Electronics, Electrical, Telecom, or VLSI Engineering
Minimum 6+ years of experience in Physical Design with mainstream P&R tools
Roles & Responsibilities:
Work on 10nm / 7nm / 5nm and below technology node designs
Solve critical customer design challenges across performance, power, and area
Develop and optimize flows/methodologies for placement, CTS, and routing
Provide training, deployment support, and technical guidance to customers
Required Technical & Professional Expertise:
Strong experience in place & route flows (placement, CTS, routing, timing optimization)
Knowledge of hierarchical designs and/or low-power implementation
Experience in Synthesis and collaboration with RTL/implementation teams
Expertise in Floorplanning (macro placement, padring, power grid, custom analog routing)
Strong understanding of STA , constraints, parasitic extraction & sign-off
Awareness of Physical Verification (DRC/LVS/DFM, chip finishing)
Interested candidates, please share your resumes:
Referrals are greatly appreciated—please feel free to forward this within your network...!
Best regards,
Maruthy Prasaad
Associate VLSI Manager - Talent Acquisition | Visakhapatnam
Eximietas Design
.
We are Hiring: Senior Physical Design Engineers / Leads / Architects / Managers.
Experience:
6-25+ Years.
Locations:
Bengaluru, India.
San Jose (Bay Area), USA.
Austin, USA.
Eligibility (USA): U. S. Permanent Residents (Green Card holders).
About the Role:
We are looking for highly experienced Senior Physical Design Leads/Managers to collaborate with top-tier semiconductor customers on advanced technology nodes.
Qualifications:
Bachelor’s or Master’s degree in Electronics, Electrical, Telecom, or VLSI Engineering
Minimum 6+ years of experience in Physical Design with mainstream P&R tools
Roles & Responsibilities:
Work on 10nm / 7nm / 5nm and below technology node designs
Solve critical customer design challenges across performance, power, and area
Develop and optimize flows/methodologies for placement, CTS, and routing
Provide training, deployment support, and technical guidance to customers
Required Technical & Professional Expertise:
Strong experience in place & route flows (placement, CTS, routing, timing optimization)
Knowledge of hierarchical designs and/or low-power implementation
Experience in Synthesis and collaboration with RTL/implementation teams
Expertise in Floorplanning (macro placement, padring, power grid, custom analog routing)
Strong understanding of STA , constraints, parasitic extraction & sign-off
Awareness of Physical Verification (DRC/LVS/DFM, chip finishing)
Interested candidates, please share your resumes:
Referrals are greatly appreciated—please feel free to forward this within your network...!
Best regards,
Maruthy Prasaad
Associate VLSI Manager - Talent Acquisition | Visakhapatnam
Eximietas Design
.
Apply for this Position
Ready to join ? Click the button below to submit your application.
Submit Application