Senior Physical Design Lead

Hi All,

Eximietas Hiring Senior Synthesis/Constraints.

Experience: 6 to 30+ Years.

📍Locations:

• India: Bengaluru, Hyderabad, Pune & Ahmedabad.
• San Jose (Bay Area), USA
• Austin, USA
• Eligibility (USA): U.S. Permanent Residents (Green Card holders).

Block / Subsystem / Partition / Full chip.

• Role: Synthesis and Timing Constraint Engineer.

• EDA Tool: Cadence Genus & Fishtail.

• Node: TSMC 3nm / 5nm.

• UPF Implementation hands-on is must.

• Synthesis PPA optimization, Hierarchical partition synthesis, Lint, Sanity Checks.

• Timing constraints generation and validation.

• Tcl, Perl, Python Scripting mandatory.

Interested Candidates please start sharing your resumes: [email protected]...