Senior Principal Engineer- Flow Innovation and Efficiency

Description

The Cadence Artisan Foundation IP group team develops industry leading Foundation IP that enable customers to tape-out their design with industry leading Power, Performance and Area. Artisan Foundation IP group develops embedded SRAMs, standard cells and general purpose IOs which can be used to build a variety of designs across different foundries with ease and meeting the best PPA. Arisan Foundation IP is used extensively in CPU compute, Automotive, Infra and High Performance Compute chips across the semiconductor industry.
We are growing our Foundation IP team and we are looking for smart, energetic, collaborative and creative people to help us lead the industry with our products. At Cadence, we believe in embracing diverse ideas and striving for excellence in all that we do. Do you want to make a difference and be challenged? Join the High-Performance Culture at Cadence.
As an individual working on the development flows, you will innovate on the efficiency of developing embedded SRAM and other memories

Responsibilities include:
• Flow innovation and improvements
• Development efficiency of embedded SRAM
• Work closely with memory engineers, software team and EDA teams to build world class development flows

• Work with teams to enable efficient ways of developing memory compilers
• Build prototypes for working efficiency

• Work closely with leading architects to enable architecture evaluation flows

• Leverage Agentic AI or existing AI-based EDA capabilities to reduce development effort

Qualifications:
• BS/MS in EE, CE or related majors
• Knowledge of embedded SRAM memory compilers
• Knowledge of characterization and EDA view generation flows
• Experience in developing efficient development flows
• Good grasp of programming languages and associated tools like python, java, make files, perl etc.

Additional recommended qualifications:
• Understanding of Foundry business and how the efficiency matters to the development
• Experience on memory validation and quality checks
• Strong knowledge of how the memories are used in customer designs
• Knowledge of EDA views in memory compilers
• Working knowledge of memory compiler development

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