Job Description
Via/ Barrier/ OEE and throughput tracking
- Partner with APC/FDC teams to deploy model-based or real-time feedback control loops to prevent excursions in critical logic modules.
Mentorship & Knowledge Management
- Train junior engineers on experimental design, chamber matching, logic-specific process sensitivities, and high-volume manufacturing methodologies.
- Develop and maintain SOPs, BKMs, control plans, and safety procedures aligned with logic foundry standards.
- Present technical reviews and readiness updates to executives, customers, and cross-functional stakeholders.
Continuous Improvement & Cost Competitiveness
- Improve cycle time, chamber utilization, and target consumption through recipe tuning, PM optimization, and hardware reliability programs.
- Drive Co O improvements by optimizing target usage, improving uptime, and collaborating with global supply-chain teams for vendor benchmarking.
- Lead cross-fab harmonization for PVD process baselines, run rules, and excursion prevention protocols.
Qualifications
Education
- Master’s or Ph. D. in Materials Science, Chemical Engineering, Electrical Engineering, Physics, or related discipline.
Experience
- 5–12 years of process engineering experience in a logic foundry or advanced-node IDM environment.
- Proven ownership of PVD processes supporting logic FEOL, MOL, and BEOL modules (e.g., contact metallization, barrier/seed deposition, capping layers, or gate stack metals).
- Strong understanding of:
- Scaled interconnect and contact challenges (Rc reduction, electromigration, TDDB, gap-fill interactions)
- Ultra-thin metal deposition for advanced design rules (
- Interface engineering and adhesion mechanisms on dielectrics, high-k, and low-k materials
- Pattern loading, AR effects, and multi-patterning integration
- Proficiency with advanced metrology (XRR, XRD, SIMS, TEM/SEM, AFM, ellipsometry, CDSEM, 3 D profilometry).
- Demonstrated ability to lead cross-functional teams, resolve high-impact excursions, and deliver stable high-volume processes.
Preferred Skills
- Experience with advanced PVD technologies such as Hi PIMS, IMP, CVD-PVD hybrid platforms, self-ionized sputtering, or nucleation engineering for ultra-thin films.
- Familiarity with logic device architecture (Planar FET, Fin FET, scaled BEOL stacks) and the corresponding metallization challenges.
- Strong documentation, presentation, and leadership skills.
- Experience coordinating work across multinational fabs or teams.
- Partner with APC/FDC teams to deploy model-based or real-time feedback control loops to prevent excursions in critical logic modules.
Mentorship & Knowledge Management
- Train junior engineers on experimental design, chamber matching, logic-specific process sensitivities, and high-volume manufacturing methodologies.
- Develop and maintain SOPs, BKMs, control plans, and safety procedures aligned with logic foundry standards.
- Present technical reviews and readiness updates to executives, customers, and cross-functional stakeholders.
Continuous Improvement & Cost Competitiveness
- Improve cycle time, chamber utilization, and target consumption through recipe tuning, PM optimization, and hardware reliability programs.
- Drive Co O improvements by optimizing target usage, improving uptime, and collaborating with global supply-chain teams for vendor benchmarking.
- Lead cross-fab harmonization for PVD process baselines, run rules, and excursion prevention protocols.
Qualifications
Education
- Master’s or Ph. D. in Materials Science, Chemical Engineering, Electrical Engineering, Physics, or related discipline.
Experience
- 5–12 years of process engineering experience in a logic foundry or advanced-node IDM environment.
- Proven ownership of PVD processes supporting logic FEOL, MOL, and BEOL modules (e.g., contact metallization, barrier/seed deposition, capping layers, or gate stack metals).
- Strong understanding of:
- Scaled interconnect and contact challenges (Rc reduction, electromigration, TDDB, gap-fill interactions)
- Ultra-thin metal deposition for advanced design rules (
- Interface engineering and adhesion mechanisms on dielectrics, high-k, and low-k materials
- Pattern loading, AR effects, and multi-patterning integration
- Proficiency with advanced metrology (XRR, XRD, SIMS, TEM/SEM, AFM, ellipsometry, CDSEM, 3 D profilometry).
- Demonstrated ability to lead cross-functional teams, resolve high-impact excursions, and deliver stable high-volume processes.
Preferred Skills
- Experience with advanced PVD technologies such as Hi PIMS, IMP, CVD-PVD hybrid platforms, self-ionized sputtering, or nucleation engineering for ultra-thin films.
- Familiarity with logic device architecture (Planar FET, Fin FET, scaled BEOL stacks) and the corresponding metallization challenges.
- Strong documentation, presentation, and leadership skills.
- Experience coordinating work across multinational fabs or teams.
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