Senior SOC Timing Engineer

Responsibilities

• Responsible for timing closure and signoff of FPGA/SoC and subsystem timing.
• Involved in static timing analysis, providing and deriving interface timing constraints to partitions, and performing final timing signoff.
• Works closely with the design and architecture team for timing convergence analysis, and with the physical design team for timing closure.

Qualifications

• Proficient in physical design industry‑standard EDA tools such as Primetime/PTPX, timing constraints development and TCL, Python.
• Good knowledge of physical design and PNR flow.
• Experience in timing signoff in 10nm or lower technology.
• BE/MS/PhD in Electronics/Electrical Engineering with 7+ years’ experience in timing closure and signoff.
• Strong communication, problem‑solving, and analytical skills.

Job Details

• Job Type: Regular
• Shift: Shift 1 (Malaysia)
• Prima...