Senior SOC Timing Signoff Engineer

A leading semiconductor company in Penang, Malaysia, is seeking a Mid-Senior level engineer for timing closure and signoff of FPGA/SoC systems. Candidates should have at least 7 years of experience, proficiency in industry-standard tools like Primetime/PTPX, and strong communication skills. This full-time role focuses on static timing analysis and collaboration with design teams. Join a dynamic environment and advance your career in semiconductor manufacturing.
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