Senior SoC Verification Engineer — UVM/RTL

A leading recruitment firm in Australia seeks a Verification Engineer to join a cutting-edge SoC design team in Adelaide. In this role, you will take ownership of verification processes for advanced designs and develop UVM-based test environments. Ideal candidates should have over 5 years of experience in digital design or SoC verification, with strong skills in System Verilog/Verilog and familiarity with industry-standard tools. Enjoy a supportive environment focused on technical excellence and career growth.
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