Job Description
We’re Hiring: STA Engineer | ACL Digital
Locations:
Bangalore & Hyderabad
Experience:
4 –10 Years
ACL Digital is looking for a
STA Engineer
with strong experience across
block and/or full-chip level
timing analysis to join our growing VLSI team.
Key Requirements:
Hands-on experience in
Block-level and/or Full-chip STA
Strong expertise in
Constraint Development
Experience with
Pre-layout and Post-layout STA
Good understanding of
Test Modes (Scan, Functional, etc.)
Ability to analyze and close timing across multiple corners and modes
What We’re Looking For:
Solid debugging and timing closure skills
Experience working in complex SoC environments
4–10 years of relevant industry experience
Interested candidates can share their resume at:
[email protected]
Feel free to tag or share with your network!
Locations:
Bangalore & Hyderabad
Experience:
4 –10 Years
ACL Digital is looking for a
STA Engineer
with strong experience across
block and/or full-chip level
timing analysis to join our growing VLSI team.
Key Requirements:
Hands-on experience in
Block-level and/or Full-chip STA
Strong expertise in
Constraint Development
Experience with
Pre-layout and Post-layout STA
Good understanding of
Test Modes (Scan, Functional, etc.)
Ability to analyze and close timing across multiple corners and modes
What We’re Looking For:
Solid debugging and timing closure skills
Experience working in complex SoC environments
4–10 years of relevant industry experience
Interested candidates can share their resume at:
[email protected]
Feel free to tag or share with your network!
Apply for this Position
Ready to join ACL Digital? Click the button below to submit your application.
Submit Application