Job Description
Role Overview
We are seeking a Senior Staff DFT Engineer to join a rapidly growing DFT design team focused on next-generation AI accelerator So Cs. In this role, you will define, architect, and implement current and future DFT/DFX solutions, supporting advanced So C designs that leverage innovative memory-centric compute and heterogeneous chiplet architectures.
This is a highly hands-on role requiring both deep technical execution and high-level planning, working across design, verification, product, and test teams to ensure robust manufacturability and silicon bring-up.
Location:
Hybrid, working onsite at our Bengaluru, Karnataka, headquarters 3-5 days per week.
Key Responsibilities
- Drive DFT partitioning strategies for ATPG, including hierarchical and scalable approaches.
- Implement ATPG compression and serialization, and perform RTL scan insertion with associated design rule fixes.
- Own Memory BIST (MBIST) solutions, including memory repair and in-system test (IST), from implementation through verification and silicon debug.
- Support boundary scan and define DFT mode constraints for IPs, providing timing feedback to STA teams.
- Generate and integrate DFT RTL, ensuring quality through RTL-level checks (e.g., linting and DFT rule verification).
- Apply and support IEEE 1149.1, IEEE 1500, and IEEE 1687 standards.
- Execute and verify ATPG (SAF, TDF) and MBIST using unit-delay and min/max timing simulations.
- Perform detailed ATPG coverage analysis and drive coverage closure.
- Collaborate with product and test engineering teams to deliver manufacturing test patterns for ATE.
- Develop diagnostic tools and flows for ATPG, MBIST, and silicon bring-up on ATE.
- Work hands-on with industry-standard DFT tools, contributing from low-level implementation through architectural planning.
We are seeking a Senior Staff DFT Engineer to join a rapidly growing DFT design team focused on next-generation AI accelerator So Cs. In this role, you will define, architect, and implement current and future DFT/DFX solutions, supporting advanced So C designs that leverage innovative memory-centric compute and heterogeneous chiplet architectures.
This is a highly hands-on role requiring both deep technical execution and high-level planning, working across design, verification, product, and test teams to ensure robust manufacturability and silicon bring-up.
Location:
Hybrid, working onsite at our Bengaluru, Karnataka, headquarters 3-5 days per week.
Key Responsibilities
- Drive DFT partitioning strategies for ATPG, including hierarchical and scalable approaches.
- Implement ATPG compression and serialization, and perform RTL scan insertion with associated design rule fixes.
- Own Memory BIST (MBIST) solutions, including memory repair and in-system test (IST), from implementation through verification and silicon debug.
- Support boundary scan and define DFT mode constraints for IPs, providing timing feedback to STA teams.
- Generate and integrate DFT RTL, ensuring quality through RTL-level checks (e.g., linting and DFT rule verification).
- Apply and support IEEE 1149.1, IEEE 1500, and IEEE 1687 standards.
- Execute and verify ATPG (SAF, TDF) and MBIST using unit-delay and min/max timing simulations.
- Perform detailed ATPG coverage analysis and drive coverage closure.
- Collaborate with product and test engineering teams to deliver manufacturing test patterns for ATE.
- Develop diagnostic tools and flows for ATPG, MBIST, and silicon bring-up on ATE.
- Work hands-on with industry-standard DFT tools, contributing from low-level implementation through architectural planning.
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