Job Description
The DFT lead works in close partnership with different teams within the FPGA business unit spanning architecture, ASIC design, verification, physical implementation, and test engineering to implement the testability features into the combined FPGA and ASIC SOC. The DFT lead will be involved from the initial investigation and feasibility to tape-out, as well as silicon validation and characterization of test methods on Automatic Test Equipment (ATE).
Responsibilities
(1.) Manage DFT requirements across architecture, design, and product teams to ensure coverage, die cost, test cost and DFT integration
requirements are met at the block and full chip level. Define, implement and validate DFT features at the FPGA full chip and sub-systems
level.
(2.) Collaborate closely with cross functional teams to support DFT insertion, synthesis, scan insertion, place-and-route, static timing analysis, timing closure, power analysis du...
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