Senior TPU RTL Design Engineer, Networking, Inter-Chip Interconnects

Senior TPU RTL Design Engineer, Networking, Inter-Chip Interconnects

_corporate_fare_ Google _place_ Sunnyvale, CA, USA

**Mid**

Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.

**Minimum qualifications:**

+ Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
+ 5 years of experience in high-performance ASIC design.
+ Experience developing networking IP across one or more layers, such as the Media Access Control (MAC), Link (L2), or Physical (PHY) layers.
+ Experience architecting or designing RTL solutions for digital systems.
+ Experience with high-speed interconnects.

**Preferred qualifications:**

+ Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architec...