Senior Verification Engineer

SEAKR is currently seeking a Verification Engineer who is responsible for developing verification and simulation strategies, conducting design reviews, creating a digital test plan and providing coverage metrics. 

• The Engineer is responsible for the construction and maintenance of simulation environments using System Verilog with UVM (Universal Verification Methodology), and performing and evaluating regression tests for a design under test. 
• The candidate must be able to extract and derive test requirements and sequences for an interface or interfaces based on available design documentation and requirements. 
• Ability to architect and construct full test environments for complex devices using UVM, including coverage, is required. 
• The candidate shall be capable of diagnosing sophisticated test failures and filing results, and be capable of analyzing code coverage to adjust agent sequence behavior. <...