Senior Verification Engineer (f/m/div)

Senior Verification Engineer (f/m/div)

Infineon Technologies invites applications for the role of Senior Verification Engineer on our R&D team.

Key Responsibilities

• Contribute to the development of SystemVerilog‑UVM test benches.
• Assist in debugging failing test cases and identifying root causes.
• Help define functional coverage models and ensure coverage goals are met.
• Collaborate in team reviews, design discussions, and process improvements.
• Support test bench quality and sign‑off targets, including coverage metrics and functional safety requirements.

Qualifications & Skills

• A bachelor’s degree in Electrical/Electronic Engineering or a related field.
• 1‑2 years of verification engineering experience, including hands‑on SystemVerilog‑UVM exposure.
• Strong understanding of verification concepts and SystemVerilog fundamentals.
• Enthusiastic about lear...