Senior Verification Engineer – SystemVerilog/UVM RTL

A leading tech company in Barcelona is looking for a Senior Verification Engineer with over 8 years of experience. The ideal candidate should have strong expertise in SystemVerilog and UVM, along with a robust background in formal and dynamic verification methodologies. In this role, you will contribute to the Verification Team to ensure the functionality of complex microprocessor architectures, develop advanced verification methodologies, and run simulations to deliver high-quality designs.
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