Job Description
Job Description:
Minimum Qualifications
• Bachelor's degree in Electronics/Electrical Engineering, Computer Science, Information Systems, or related field.
• 5+ years Hardware Engineering experience or related work experience.
Responsibilities:
• You will be part of Qualcomm Snapdragon So C - Silicon Validation team, particularly in the bring up of SVE convex infra, IST framework for the enablement of VI content in production.
• You will be working with IP validation teams and Systems validation Lead/system content engineer for bringup the framework.
• Own So C frequent regression and execute end-to-end regression suite by considering So C design corner cases wrt power and performance. Executing these releases on bench in lab and supporting the DFT, SLT teams in Debug and enabling different features in the framework.
• Work with a relevant team members for regular reporting of issues and failure debugs.
• Understand the IP architecture, work with IP validation teams and Systems validation Lead/system content engineer to understand the validation requirements, develop/port/enhance the validation software content and bring up.
• Use silicon debug hooks to measure power/performance/coverage and other KPI metrics
Mandatory Skills:
• Basics of processor architecture, Multicore/Multiprocessor with SMP/MTE/heterogenous cores.
• C language expertise for low level programming, Assembly language for any processor, C-assembly interworking
• Operating systems/RTOS/Linux kernel internals, scheduling policies, locking mechanism, MMU/paging etc
• Exposure to working on emulation/pre-si environment is added advantage
• Using JTAG based debuggers, compilers/linkers
• Should have good exposure to software development life cycle
Desired Skills
• Exposure to So C architecture paradigms – interconnects, power management,
• Software development for silicon enablement, silicon validation
• Bring-up of hardware-software solution on FPGA/emulation platforms and on fresh SOC designs
• Software for power/performance KPIs
• Good knowledge of ARM Cortex-A7/A8) / x86 / Power PC CPU and memory system architecture
• Weakly ordered memory model/pipelining of memory systems/memory barriers
• Software development towards higher performance of multi-threaded applications using lower power
• Top level of ASIC design methodology is an added skill
• Extraordinary debugging skills using JTGA / any serial wire debuggers or Emulators on both C & Assembly programming.
• Working exposure on Make files, linker scripts and cross compilers.
Preferred Qualifications
• Exposure to So C architecture paradigms interconnects, power management, DFT,
• Operating systems/RTOS/Linux kernel internals. Exposure to configuration Management tools (Perforce/SVN/GIT).
• Bring-up of hardware-software solution on FPGA/emulation platforms and on fresh SOC designs
• Operating and automation knowledge of measurement instrumentation
Minimum Qualifications
• Bachelor's degree in Electronics/Electrical Engineering, Computer Science, Information Systems, or related field.
• 5+ years Hardware Engineering experience or related work experience.
Responsibilities:
• You will be part of Qualcomm Snapdragon So C - Silicon Validation team, particularly in the bring up of SVE convex infra, IST framework for the enablement of VI content in production.
• You will be working with IP validation teams and Systems validation Lead/system content engineer for bringup the framework.
• Own So C frequent regression and execute end-to-end regression suite by considering So C design corner cases wrt power and performance. Executing these releases on bench in lab and supporting the DFT, SLT teams in Debug and enabling different features in the framework.
• Work with a relevant team members for regular reporting of issues and failure debugs.
• Understand the IP architecture, work with IP validation teams and Systems validation Lead/system content engineer to understand the validation requirements, develop/port/enhance the validation software content and bring up.
• Use silicon debug hooks to measure power/performance/coverage and other KPI metrics
Mandatory Skills:
• Basics of processor architecture, Multicore/Multiprocessor with SMP/MTE/heterogenous cores.
• C language expertise for low level programming, Assembly language for any processor, C-assembly interworking
• Operating systems/RTOS/Linux kernel internals, scheduling policies, locking mechanism, MMU/paging etc
• Exposure to working on emulation/pre-si environment is added advantage
• Using JTAG based debuggers, compilers/linkers
• Should have good exposure to software development life cycle
Desired Skills
• Exposure to So C architecture paradigms – interconnects, power management,
• Software development for silicon enablement, silicon validation
• Bring-up of hardware-software solution on FPGA/emulation platforms and on fresh SOC designs
• Software for power/performance KPIs
• Good knowledge of ARM Cortex-A7/A8) / x86 / Power PC CPU and memory system architecture
• Weakly ordered memory model/pipelining of memory systems/memory barriers
• Software development towards higher performance of multi-threaded applications using lower power
• Top level of ASIC design methodology is an added skill
• Extraordinary debugging skills using JTGA / any serial wire debuggers or Emulators on both C & Assembly programming.
• Working exposure on Make files, linker scripts and cross compilers.
Preferred Qualifications
• Exposure to So C architecture paradigms interconnects, power management, DFT,
• Operating systems/RTOS/Linux kernel internals. Exposure to configuration Management tools (Perforce/SVN/GIT).
• Bring-up of hardware-software solution on FPGA/emulation platforms and on fresh SOC designs
• Operating and automation knowledge of measurement instrumentation
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