SoC Design Verification Engineer

This role is about seeing the whole chip work, not just pieces. You’ll verify subsystems and full SoCs that actually tape out. If system-level bugs don’t scare you, you’ll enjoy this.

Work,

• Verify full-chip SoCs or large subsystems

• Develop or own key UVM TB components

• Create SoC-level testplans from specs

• Run JasperGold for connectivity checks

• Close toggle coverage at SoC level

Must-Have Experience

• Majority experience in SoC or subsystem DV

• Strong debugging with Verdi / Verisium / SimVision

• JasperGold connectivity checks experience is mandatory

Cheers,

Shahid