SOC Design Verification Engineer

Talent Acquisition @ UST | Talent Sourcing, Recruitment Strategies

Job Description:

• Execute SoC verification tasks and work closely with team members to review and understand relevant functional and safety-related requirements.
• Work and align with different stakeholders to identify verification plans and define SOC verification strategies.
• Execute the verification plan by developing C/C++ test cases and System Verilog/UVM testbench components and by integrating 3rd party VIP components.

Job Requirements:

• Masters/Bachelors in Electrical Engineering or Computer Science with more than 5 years of relevant work experience.
• Understand the usage of tools like Xcelium, Spectre(X), and SimVision.
• Strong foundational knowledge of digital/mixed-signal design & verification.
• Knowledge and hands-on experience of System Verilog and UVM.
• Exposure to version-controlling (e.g., Git...