SoC/ASIC Design Engineer

Emerging state-of-the-art microelectronic technologies and electronics design methodologies are promising to revolutionize the way we design and implement readout and control circuits for on-detector electronics in particle physics experiments.

CERN and its EP-ESE/ME section are actively exploring the feasibility of utilizing RISC-V processing cores and System-on-Chip (SoC) design methodologies for future on-detector electronics.

• You have a professional background in Electronics Engineer (or a related field) and have either:
  • aMaster's degree with 2 to 6 years of post-graduation professional experience;
  • or aPhD with no more than 3 years of post-graduation professional experience.
• You have never had a CERN fellow or graduate contract before.