(Sr.) ISP RTL Design Manager

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Responsibilities:

• Implement ISP Algorithm into hardware using Verilog, SystemVerilog, and/or SystemC (High Level Synthesis).
• Define ISP hardware architecture based on product features and performance requirements, including gate count and power estimation.
• Verify logic at ISP level and digital system level.
• Optimize design for reduced gate count and low power consumption.
• Drive ISP design activities in collaboration with ISP Algorithm Team, ISP Design leaders across sites, and Digital System Design Team.
• Lead, supervise, and mentor a team of RTL design engineers.

Requirements:

• Minimum MSEE, BSEE, or equivalent, with 7+ years of digital design and verification experience.
• 3+ years of project management or peo...