Job Description
Top100 Global Semiconductor Organization HQ in California. Revenue over 200 Million USD
Location: Bangalore
The Sr. Layout Design Engineer will lead top-level chip-planning and perform block-level custom layouts for CMOS and BiCMOS circuits. The Sr. Layout Design Engineer will review, and coordinate work content performed by offshore layout designers. Train junior layout engineers and offshore layout contractors. Contribute to develop standard layout methodologies across site. Contribute to build process and procedures to achieve high layout quality
Responsibilities:
- Requires remote interfacing with local and global design and layout teams in multiple design centers across different time zones
- Lead Top-level chip-planning and perform functional-block-level, block-level, sub-block level, leaf cell, standard cell custom layouts for CMOS and BiCMOS circuits
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