Job Description

Sr. Principal Design Engineer – Cadence

Location: Av Contorno 5800, Belo Horizonte, Minas Gerais, Brazil. Full‑time, 40 hours/week.

Job Description

  • Work with ASIC Design Verification flow.
  • Daily activities related with Simulation DV, Emulation, Post Silicon Bringup Validation.

Requirements

  • Complete Bachelor's degree in Electrical Engineering, Computer Science or related areas.
  • Strong expertise in building test‑benches using System‑Verilog, UVM, C/C++.
  • Strong digital logic fundamentals and understanding.
  • Experience in functional coverage/code coverage/assertions (SVA) development and closure.
  • Strong debug skills.
  • Should have gone through complete lifecycle of ASIC productization.
  • Experience in using emulation or post silicon desirable but not mandatory.
  • Proficient in scripting/automation using any standard scripting language like Perl/Py...

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