Sr Staff Design Verification Engineer

• Plan the verification of complex SoC & design blocks by fully understanding the design specification

• Interact with design/system engineers to identify important verification scenarios

• Create and enhance constrained-random verification environments using System Verilog.

• Create and support UVM compliant test-bench architecture

• Formally verify designs with SVA and industry leading formal tools

• Identify and write various coverage metrics for stimulus and corner-cases

• Build reusable DV infrastructure components for both block and top-level environments

• Debug tests in collaboration with design engineering staff

• Build verification tools for system automation, regressions, and reporting

• BS/MSEE & relevant work experience

• Experience with System Verilog, SVA and functional coverage

• Deep understanding of event-driven simulator-based modeling techniques