Job Description
Job Title: Static Timing Analysis (STA) Engineer
Job Overview
We are looking for a highly skilled Static Timing Analysis (STA) Engineer to join our ASIC/So C design team. The ideal candidate will be responsible for performing timing analysis, developing constraints, and driving timing closure across multiple design stages. This role requires strong technical expertise, problem-solving skills, and cross-functional collaboration.
Key Responsibilities
- Perform Static Timing Analysis (setup, hold, recovery, removal) across all PVT corners and modes.
- Create, refine, and validate SDC constraints including clocks, generated clocks, false paths, and multi-cycle paths.
- Drive timing closure during synthesis, place & route, and final signoff.
- Debug timing violations related to clocking, logic depth, routing, buffering, and cell sizing.
- Work closely with RTL, Physical Design, CTS, and DFT teams to resolve timing issues.
- Run STA using tools such as Synopsys Prime Time or Cadence Tempus.
- Analyze SI/crosstalk, OCV/AOCV/POCV, and apply advanced timing methodologies.
- Ensure full timing signoff criteria are met before tape-out.
Required Qualifications
- 3–10 years of hands-on STA experience (can adjust based on your needs).
- Bachelor’s or Master’s in Electrical Engineering, Electronics, VLSI, or related field.
- Strong understanding of digital logic, timing concepts, and CMOS fundamentals.
- Experience with Prime Time, Tempus, ICC2, Fusion Compiler, or Innovus.
- Solid knowledge of SDC, timing exceptions, and multi-clock domain analysis.
- Proficiency in Tcl, with additional scripting (Python/Perl) being a plus.
Preferred Skills
- Experience with So C-level STA and hierarchical timing flows.
- Knowledge of clock tree synthesis (CTS) and clock architecture.
- Familiarity with low-power design (UPF/CPF).
- Understanding of DFT timing, scan modes, and test constraints.
Soft Skills
- Strong analytical and debugging abilities.
- Excellent communication and documentation skills.
- Ability to work in a fast-paced, cross-functional environment.
Job Overview
We are looking for a highly skilled Static Timing Analysis (STA) Engineer to join our ASIC/So C design team. The ideal candidate will be responsible for performing timing analysis, developing constraints, and driving timing closure across multiple design stages. This role requires strong technical expertise, problem-solving skills, and cross-functional collaboration.
Key Responsibilities
- Perform Static Timing Analysis (setup, hold, recovery, removal) across all PVT corners and modes.
- Create, refine, and validate SDC constraints including clocks, generated clocks, false paths, and multi-cycle paths.
- Drive timing closure during synthesis, place & route, and final signoff.
- Debug timing violations related to clocking, logic depth, routing, buffering, and cell sizing.
- Work closely with RTL, Physical Design, CTS, and DFT teams to resolve timing issues.
- Run STA using tools such as Synopsys Prime Time or Cadence Tempus.
- Analyze SI/crosstalk, OCV/AOCV/POCV, and apply advanced timing methodologies.
- Ensure full timing signoff criteria are met before tape-out.
Required Qualifications
- 3–10 years of hands-on STA experience (can adjust based on your needs).
- Bachelor’s or Master’s in Electrical Engineering, Electronics, VLSI, or related field.
- Strong understanding of digital logic, timing concepts, and CMOS fundamentals.
- Experience with Prime Time, Tempus, ICC2, Fusion Compiler, or Innovus.
- Solid knowledge of SDC, timing exceptions, and multi-clock domain analysis.
- Proficiency in Tcl, with additional scripting (Python/Perl) being a plus.
Preferred Skills
- Experience with So C-level STA and hierarchical timing flows.
- Knowledge of clock tree synthesis (CTS) and clock architecture.
- Familiarity with low-power design (UPF/CPF).
- Understanding of DFT timing, scan modes, and test constraints.
Soft Skills
- Strong analytical and debugging abilities.
- Excellent communication and documentation skills.
- Ability to work in a fast-paced, cross-functional environment.
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