Job Description
Role Summary:As a key player on the Digital Design team, you will participate in the RTL design and development of the signal processing path for Aeva's 4-D Lidar processing chip. You will be responsible for implementing and/or integrating sub-components of the design in ASICs and FPGAs.
What you'll be doing:- Develop custom sub-components of the digital signaling pipeline like filters, FFTs, control logic, etc
- Write micro-architecture specifications, Code RTL, Test & Validate Aeva-specific sub-components
- Implement additional functionality including functional safety and robustness functions
- Focus on developing efficient, highly reliable, highly available, robust functionality
- Work with Architects, design engineers, verification engineers, and System software teams to ensure that the SOC meets its functional, performance, and power targets
What you'll have:
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