Staff Design Verification

Job Responsibilities:
Verification of complex designs such as accelerators/ datapath IP, processor core subsystems, complex interfaces/ protocols such as DDR/ Ethernet/ USB etc using leading edge methodologies like UVM & Formal DV
Architect the testbench and develop the verification environment in UVM and Formal based verification approaches
Define testplan, tests and verification methodology for block / sub-system level verification. Work with design team in generating test-plans and closure of code and functional coverage. Integrate the block testbench at sub-system level UVM environment and verify integration. Interact with analog co-sim and firmware team in enabling toplevel chip verification aspects
Package verification environment for Digital IP for seamless integration into verification flow at different stages of execution
Evaluate 3rd party IPs on key qualitative aspects such as design quality, robustness of Design Verification (DV) practice, ease of DV env...